1. Field of the Invention
The present invention relates to a semiconductor memory device having spare memory cells for repairing defects in normal memory cells and, more particularly, to checking spare memory cells for defects.
2. Description of the Background Art
FIG. 30 is a plan view of principal portions of a conventional dynamic semiconductor memory device (referred to hereinafter as a DRAM). In FIG. 30, the reference numeral 141 designates an area wherein a column of sense amplifiers are arranged (a sense amplifier forming area); 142 designates an area wherein a group of memory elements are arranged (memory cell array); 143 designates a row decoder for activating a word line specified by a row address signal for selecting a cell in the memory cell array 142; and 144 designates a column decoder for activating a bit line specified by a column address signal for selecting a cell in the memory cell array 142.
FIG. 31 conceptually illustrates the structure of an area 145 shown in FIG. 30. In FIG. 31, the reference numeral 146 designates memory cells for constituting the memory cell array 142; the reference character 147a designates word lines provided in respective rows of the normal memory cells and controlled by a normal row decoder 143a so that they are active/inactive; 147b designates a word line provided in a spare cell row in which spare memory cells are arranged and controlled by a spare decoder 143b so that it is active/inactive; 148a designates bit lines provided in respective normal columns in which the normal memory cells are arranged and controlled by a normal column decoder 144a of the column decoder 144 so that they are active/inactive; and 148b designates bit lines provided in respective spare memory cell columns in which the spare memory cells are arranged and controlled by a spare column decoder 144b of the column decoder 144 so that they are active/inactive.
The DRAM shown in FIG. 31 has a redundant construction for repairing a defect. Each memory cell array 142 includes one or more spare rows and one or more spare columns. If a memory cell is defective, the row or column containing the defect is electrically replaced with a spare row or spare column by the laser fuse programming or the like to repair the defect.
FIG. 32 is a plan view of a conventional dynamic semiconductor memory device. In FIG. 32, the reference numeral 200 designates a storage area of the dynamic semiconductor memory device; 201 designates an area wherein a column of sense amplifiers are arranged (a sense amplifier forming area); 202 designates an area wherein a group of memory elements formed between the areas 201 wherein a plurality of columns of sense amplifiers are arranged respectively are arranged; 203 designates word line backing areas for connecting metal interconnecting lines having a relatively low resistance; and 204 designates areas wherein interconnecting lines having a relatively high resistance are formed in a layer different from the word line backing areas 203 and intersecting the sense amplifier forming areas 201.
FIG. 33 conceptually illustrates the structure of the word line backing areas 203 shown in FIG. 32. In FIG. 33, the reference numeral 205 designates aluminum interconnecting lines having a relatively low resistance; and 206 designates polycide interconnecting lines having a relatively high resistance and connected in parallel with the aluminum interconnecting lines 205.
FIG. 34 is a block diagram of a memory cell block of the dynamic semiconductor memory device. In FIG. 34, the reference characters 141a and 141c designate sense amplifier forming areas wherein sense amplifiers for reading data from the normal memory cells are formed; 141b and 141d designate sense amplifier forming areas wherein sense amplifiers for reading data from the spare memory cells are formed; 148c designates bit line pairs for transmitting data read from the normal memory cells; and 148d designates bit line pairs for transmitting data read from the spare memory cells. Like reference numerals and characters are used to designate elements corresponding to those of FIG. 31.
The conventional semiconductor memory device constructed as above described has failed to effectively repair defects in the memory cells arranged in the spare rows and spare columns.
A first aspect of the present invention is intended for a semiconductor memory device switchable between a normal mode wherein normal memory cells are read/written and a test mode wherein the normal memory cells and spare memory cells provided for repairing a defect in the normal memory cells are tested for a defect. According to the present invention, the semiconductor memory device comprises: a memory cell array including normal rows and normal columns in which the normal memory cells are arranged, and at least one spare memory cell row and at least one spare memory cell column in which the spare memory cells are arranged; a normal row decoder and a normal column decoder for accessing the normal memory cells; a spare row decoder for selecting the at least one spare memory cell row in the normal modes; and a spare column decoder for selecting the at least one spare memory cell column in the normal mode, wherein an address signal for addressing the memory cell array is used in the test mode to put at least one of the at least one spare memory cell row and the at least one spare memory cell column into a selected state without using the spare row decoder and the spare column decoder.
Preferably, according to a second aspect of the present invention, the semiconductor memory device further comprises access means for accessing a first spare memory cell selected by the normal row decoder and the spare column decoder, a second spare memory cell selected by the normal column decoder and the spare row decoder, and a third spare memory cell selected by the spare row decoder and the spare column decoder in the test mode.
Preferably, according to a third aspect of the present invention, the access means decodes a normal row address signal and a normal column address signal for selecting the normal memory cells in the normal mode to select the first to third spare memory cells in the test mode.
Preferably, according to a fourth aspect of the present invention, the access means includes: a first test row decoder for decoding the normal row address signal to select the normal rows in the test mode; a second test row decoder for decoding the normal row address signal to select the at least one spare memory cell row in the test mode; a first test column decoder for decoding the normal column address signal to select the normal columns in the test mode; a second test column decoder for decoding the normal column address signal to select the at least one spare memory cell column in the test mode; and control means for setting a first condition in which the first test row decoder and the first test column decoder are operated, a second condition in which the first test row decoder and the second column decoder are operated, a third condition in which the second test row decoder and the first test column decoder are operated, and a fourth condition in which the second test row decoder and the second test column decoder are operated.
Preferably, according to a fifth aspect of the present invention, the access means includes: converting means for converting the normal row address signal and the normal column address signal to produce a test row address signal and a test column address signal in the test mode; a test row decoder for decoding the test row address signal to select the normal rows and the at least one spare memory cell row in the test mode; and a test column decoder for decoding the test column address signal to select the normal columns and the at least one spare memory cell column in the test mode.
Preferably, according to a sixth aspect of the present invention, the access means decodes a normal address signal for selecting the normal memory cells in the normal mode and an additional address signal added to the normal address signal to select the normal memory cells and the first to third spare memory cells in the test mode.
Preferably, according to a seventh aspect of the present invention, the access means performs switching between the normal mode and the test mode in response to a control signal, and is set to the normal mode when the control signal is not applied thereto.
Preferably, according to an eighth aspect of the present invention, the access means shares a portion thereof having an arrangement similar to that of the normal row decoder with the normal row decoder and shares a portion thereof having an arrangement similar to that of the normal column decoder with the normal column decoder in the normal mode and the test mode.
Preferably, according to a ninth aspect of the present invention, input timing of an address signal in the test mode to the access means is substantially set equal to input timing of the normal row address signal to the normal row decoder and the normal column address signal to the normal column decoder in the normal mode.
According to a tenth aspect of the present invention, a semiconductor memory device comprises: a memory cell array including normal rows and normal columns in which normal memory cells are arranged, and at least one spare memory cell row and at least one spare memory cell column in which spare memory cells are arranged; and access means for accessing the spare memory cells arranged in the at least one spare memory cell row and the at least one spare memory cell column of the memory cell array for repairing a defect, wherein the same data are simultaneously written into a plurality of spare memory cells in a mode in which the spare memory cells are accessed.
An eleventh aspect of the present invention is intended for a method of checking a semiconductor memory device for a defect, the semiconductor memory device being switchable between a normal mode in which normal memory cells are read/written and a test mode in which the normal memory cells and spare memory cells provided for repairing a defect in the normal memory cells are tested, the semiconductor memory device comprising a memory cell array including normal rows and normal columns in which the normal memory cells are arranged and at least one spare memory cell row and at least one spare memory cell column in which the spare memory cells are arranged, a normal row decoder and a normal column decoder for accessing the normal memory cells, a spare row decoder for selecting the at least one spare memory cell row, and a spare column decoder for selecting the at least one spare memory cell column. According to the present invention, the method comprises the steps of: testing the normal memory cells; testing a spare memory cell selected by the normal row decoder and the spare column decoder; testing a spare memory cell selected by the normal column decoder and the spare row decoder; and testing a spare memory cell selected by the spare row decoder and the spare column decoder.
The semiconductor memory device in accordance with the first aspect of the present invention is designed so that at least one of the at least one spare memory cell row and the at least one spare memory cell column is put into the selected state with normal-mode timing without using the spare row decoder and the spare column decoder by using the address signal for addressing the memory cell array in the test mode. Thus, the address signal for use in the normal mode may be used for the test in the test mode without changing the conventional arrangement for reading and writing data from the normal memory cells and spare memory cells. Less portions are required to change in order to add the function of testing the spare memory cells.
In accordance with the semiconductor memory device of the second aspect of the present invention, the access means may access the third spare memory cell, reducing the number of failures of the semiconductor memory device which are generated when the defective normal memory cells are replaced with the spare memory cells.
The semiconductor memory device in accordance with the third aspect of the present invention does not necessitate the address signal provided specifically for the selection of addresses of the spare memory cells in the test mode to reduce the number of addresses specified by the address signal, reducing the circuit scale for input/output of the address signal in the normal mode.
The semiconductor memory device in accordance with the fourth aspect of the present invention may use the first and second test row decoders and the first and second test column decoders to test all memory cells in the memory cell array by the control means using the normal row address signal and the normal column address signal in the test mode. This reduces the number of addresses specified by the address signal provided from the exterior.
In accordance with the semiconductor memory device of the fifth aspect of the present invention, the converting means converts the normal row address signal and the normal column address signal to generate the test row address signal to be provided to the test row decoder and the test column address signal to be provided to the test column decoder. This reduces the number of addresses specified by the address signal provided from the exterior.
In accordance with the semiconductor memory device of the sixth aspect of the present invention, the additional address signal is added to the normal address signal when the address signal for selecting the first to third spare memory cells is generated. This reduces the number of addresses specified by the address signal provided from the exterior.
The semiconductor memory device in accordance with the seventh aspect of the present invention is set to the normal mode when the control signal is not inputted thereto, eliminating the need for setting to the normal mode when the semiconductor memory device is finished.
In accordance with the semiconductor memory device of the eighth aspect of the present invention, the access means is constructed to share the portion thereof having the arrangement similar to that of the normal row decoder with the normal row decoder and to share the portion thereof having the arrangement similar to that of the normal column decoder with the normal column decoder. This simplifies the arrangement.
In accordance with the semiconductor memory device of the ninth aspect of the present invention, the input of the address signal provided in the test mode to the access means is substantially timed to the input of the normal row address signal to be applied to the normal row decoder and the normal column address signal to be applied to the normal column decoder in the normal mode. The signal may be provided in a similar manner in the normal mode and test mode, and is easy to handle.
The semiconductor memory device in accordance with the tenth aspect of the present invention simultaneously writes the same data into the plurality of spare memory cells to prepare the test of the spare memory cells for a short time.
The method of checking a semiconductor memory device for a defect in accordance with the eleventh aspect of the present invention may test the spare memory cells selected by the spare row decoder and the spare column decoder, reducing the number of failures generated in the semiconductor memory device after the replacement.
It is therefore an object of the present invention to provide a semiconductor memory device which is capable of effectively repairing a defect in some of the memory cells arranged in a plurality of spare rows or columns. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.